research
∙
03/13/2021
Design Principles for Packet Deparsers on FPGAs
The P4 language has drastically changed the networking field as it allow...
share
research
∙
10/01/2020
CARLA: A Convolution Accelerator with a Reconfigurable and Low-Energy Architecture
Convolutional Neural Networks (CNNs) have proven to be extremely accurat...
research
∙
04/16/2020
Bridging the Gap: FPGAs as Programmable Switches
The emergence of P4, a domain specific language, coupled to PISA, a doma...
research
∙
02/23/2020
PoET-BiN: Power Efficient Tiny Binary Neurons
The success of neural networks in image classification has inspired vari...
research
∙
02/15/2020
An Energy-Efficient Accelerator Architecture with Serial Accumulation Dataflow for Deep CNNs
Convolutional Neural Networks (CNNs) have shown outstanding accuracy for...
research
∙
03/05/2019
Module-per-Object: a Human-Driven Methodology for C++-based High-Level Synthesis Design
High-Level Synthesis (HLS) brings FPGAs to audiences previously unfamili...
research
∙
11/24/2017
SHIP: A Scalable High-performance IPv6 Lookup Algorithm that Exploits Prefix Characteristics
Due to the emergence of new network applications, current IP lookup engi...
research
∙
11/17/2017
P4-compatible High-level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs
Packet parsing is a key step in SDN-aware devices. Packet parsers in SDN...
research
∙
12/06/2016
Memory Efficient Multi-Scale Line Detector Architecture for Retinal Blood Vessel Segmentation
This paper presents a memory efficient architecture that implements the ...
research
∙
09/25/2016
