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06/15/2023
MLonMCU: TinyML Benchmarking with Fast Retargeting
While there exist many ways to deploy machine learning models on microco...
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03/31/2023
Fused Depthwise Tiling for Memory Optimization in TinyML Deep Neural Network Inference
Memory optimization for deep neural network (DNN) inference gains high r...
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12/29/2022
Biologically Plausible Learning on Neuromorphic Hardware Architectures
With an ever-growing number of parameters defining increasingly complex ...
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09/20/2021
Differentially Evolving Memory Ensembles: Pareto Optimization based on Computational Intelligence for Embedded Memories on a System Level
As the relative power, performance, and area (PPA) impact of embedded me...
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03/05/2020
Predicting Memory Compiler Performance Outputs using Feed-Forward Neural Networks
Typical semiconductor chips include thousands of mostly small memories. ...
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03/02/2020
TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix)
With recent advances in reverse engineering, attackers can reconstruct a...
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05/14/2017
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning
At submicron manufacturing technology nodes, pro- cess variations affect...
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05/14/2017
PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model
In static timing analysis, clock-to-q delays of flip-flops are considere...
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05/14/2017
EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers
At nanometer manufacturing technology nodes, process variations signific...
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05/14/2017
Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability
At submicron manufacturing technology nodes process variations affect ci...
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05/14/2017
Statistical Timing Analysis and Criticality Computation for Circuits with Post-Silicon Clock Tuning Elements
Post-silicon clock tuning elements are widely used in high-performance d...
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05/14/2017
ILP-based Alleviation of Dense Meander Segments with Prioritized Shifting and Progressive Fixing in PCB Routing
Length-matching is an important technique to bal- ance delays of bus sig...
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05/14/2017
Post-Route Alleviation of Dense Meander Segments in High-Performance Printed Circuit Boards
Length-matching is an important technique to balance delays of bus signa...
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05/14/2017
Post-Route Refinement for High-Frequency PCBs Considering Meander Segment Alleviation
In this paper, we propose a post-processing framework which iteratively ...
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05/14/2017
On Timing Model Extraction and Hierarchical Statistical Timing Analysis
In this paper, we investigate the challenges to apply Statistical Static...
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05/14/2017
Statistical Timing Analysis for Latch-Controlled Circuits with Reduced Iterations and Graph Transformations
Level-sensitive latches are widely used in high- performance designs. Fo...
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05/14/2017
Fast Statistical Timing Analysis for Circuits with Post-Silicon Tunable Clock Buffers
Post-Silicon Tunable (PST) clock buffers are widely used in high perform...
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05/14/2017
Timing Model Extraction for Sequential Circuits Considering Process Variations
As semiconductor devices continue to scale down, process vari- ations be...
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05/14/2017
On Hierarchical Statistical Static Timing Analysis
Statistical static timing analysis deals with the increasing variations ...
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05/07/2017
