ForASec: Formal Analysis of Security Vulnerabilities in Sequential Circuits
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Security vulnerability analysis of Integrated Circuits using conventional design-time validation and verification techniques is generally a computationally intensive task and incomplete by nature, under limited resources and time. To overcome this limitation, we propose a novel methodology based on model checking to formally analyze security vulnerabilities in sequential circuits considering side-channel parameters like propagation delay, switching and leakage power. In particular, we present a novel algorithm to efficiently partition the state-space into corresponding smaller state-spaces for faster security analysis of complex sequential circuits and thereby mitigating the associated state-space explosion due to their feedback loops. We analyze multiple ISCAS89 and trust-hub benchmarks to demonstrate the efficacy of our framework in identifying security vulnerabilities.
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