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11/19/2022
Accuracy Boosters: Epoch-Driven Mixed-Mantissa Block Floating-Point for DNN Training
The unprecedented growth in DNN model complexity, size and the amount of...
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03/22/2022
Scale-out Systolic Arrays
Multi-pod systolic arrays are emerging as the architecture of choice in ...
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10/19/2020
Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation
Graphics Processing Units (GPUs) employ large register files to accommod...
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01/20/2020
SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators
Virtual memory (VM) is critical to the usability and programmability of ...
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03/05/2019
SMoTherSpectre: exploiting speculative execution through port contention
Spectre, Meltdown, and related attacks have demonstrated that kernels, h...
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09/16/2018
Exploiting Errors for Efficiency: A Survey from Circuits to Algorithms
When a computational task tolerates a relaxation of its specification or...
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04/04/2018
Training DNNs with Hybrid Block Floating Point
The wide adoption of DNNs has given birth to unrelenting computing requi...
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04/04/2018
End-to-End DNN Training with Block Floating Point Arithmetic
DNNs are ubiquitous datacenter workloads, requiring orders of magnitude ...
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01/20/2018
Design Guidelines for High-Performance SCM Hierarchies
With emerging storage-class memory (SCM) nearing commercialization, ther...
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01/20/2018
Enabling Storage Class Memory as a DRAM Replacement for Datacenter Services
With emerging storage-class memory (SCM) nearing commercialization, ther...
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01/20/2018
Storage-Class Memory Hierarchies for Servers
With emerging storage-class memory (SCM) nearing commercialization, ther...
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01/20/2018
Storage-Class Memory Hierarchies for Scale-Out Servers
With emerging storage-class memory (SCM) nearing commercialization, ther...
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12/01/2016