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11/20/2022
TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs
Prior works propose SRAM-based TRNGs that extract entropy from SRAM arra...
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11/10/2022
DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips
To understand and improve DRAM performance, reliability, security and en...
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09/21/2022
HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips
DRAM is the building block of modern main memory systems. DRAM cells mus...
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07/27/2022
Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture
There are two major sources of inefficiency in computing systems that us...
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07/15/2022
ERIC: An Efficient and Practical Software Obfuscation Framework
Modern cloud computing systems distribute software executables over a ne...
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06/01/2022
PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques
DRAM-based main memory is used in nearly all computing systems as a majo...
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01/04/2022
DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators
Random number generation is an important task in a wide variety of criti...
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10/29/2021
PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM
Processing-using-memory (PuM) techniques leverage the analog operation o...
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10/12/2021
MoRS: An Approximate Fault Modelling Framework for Reduced-Voltage SRAMs
On-chip memory (usually based on Static RAMs-SRAMs) are crucial componen...
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05/19/2021
QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips
True random number generators (TRNG) sample random physical processes to...
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05/04/2020
An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration
We empirically evaluate an undervolting technique, i.e., underscaling th...
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12/01/2019
A Novel FPGA-Based High Throughput Accelerator For Binary Search Trees
This paper presents a deeply pipelined and massively parallel Binary Sea...
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05/08/2018
Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency
This paper summarizes the idea of ChargeCache, which was published in HP...
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05/08/2018
SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure
This paper summarizes the SoftMC DRAM characterization infrastructure, w...
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04/06/2016