Hierarchical decoding to reduce hardware requirements for quantum computing

by   Nicolas Delfosse, et al.

Extensive quantum error correction is necessary in order to scale quantum hardware to the regime of practical applications. As a result, a significant amount of decoding hardware is necessary to process the colossal amount of data required to constantly detect and correct errors occurring over the millions of physical qubits driving the computation. The implementation of a recent highly optimized version of Shor's algorithm to factor a 2,048-bits integer would require more 7 TBit/s of bandwidth for the sole purpose of quantum error correction and up to 20,000 decoding units. To reduce the decoding hardware requirements, we propose a fault-tolerant quantum computing architecture based on surface codes with a cheap hard-decision decoder, the lazy decoder, combined with a sophisticated decoding unit that takes care of complex error configurations. Our design drops the decoding hardware requirements by several orders of magnitude assuming that good enough qubits are provided. Given qubits and quantum gates with a physical error rate p=10^-4, the lazy decoder drops both the bandwidth requirements and the number of decoding units by a factor 50x. Provided very good qubits with error rate p=10^-5, we obtain a 1,500x reduction in bandwidth and decoding hardware thanks to the lazy decoder. Finally, the lazy decoder can be used as a decoder accelerator. Our simulations show a 10x speed-up of the Union-Find decoder and a 50x speed-up of the Minimum Weight Perfect Matching decoder.


page 1

page 2

page 3

page 4


A Scalable Decoder Micro-architecture for Fault-Tolerant Quantum Computing

Quantum computation promises significant computational advantages over c...

Trapping Sets of Quantum LDPC Codes

Iterative decoders for finite length quantum low-density parity-check (Q...

LILLIPUT: A Lightweight Low-Latency Lookup-Table Based Decoder for Near-term Quantum Error Correction

The error rates of quantum devices are orders of magnitude higher than w...

Better Than Worst-Case Decoding for Quantum Error Correction

The overheads of classical decoding for quantum error correction on supe...

Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories through Optimal Design of BCH Codes

The size reduction of transistors in the latest flash memory generation ...

Microarchitectures for Heterogeneous Superconducting Quantum Computers

Noisy Intermediate-Scale Quantum Computing (NISQ) has dominated headline...

A Scalable, Fast and Programmable Neural Decoder for Fault-Tolerant Quantum Computation Using Surface Codes

Quantum error-correcting codes (QECCs) can eliminate the negative effect...

Please sign up or login with your details

Forgot password? Click here to reset