Variable Instruction Fetch Rate to Reduce Control Dependent Penalties

07/14/2017

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by   Aswin Ramachandran, et al.

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In order to overcome the branch execution penalties of hard-to-predict instruction branches, two new instruction fetch micro-architectural methods are proposed in this paper. In addition, to compare performance of the two proposed methods, different instruction fetch policy schemes of existing multi-branch path architectures are evaluated. An improvement in Instructions Per Cycle (IPC) of 29.4 predictor on SPEC 2000/2006 benchmark is shown. In this paper, wide pipeline machines are simulated for evaluation purposes. The methods discussed in this paper can be extended to High Performance Scientific Computing needs, if the demands of IPC improvement are far more critical than cost.