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12/13/2022
ALP: Alleviating CPU-Memory Data Movement Overheads in Memory-Centric Systems
Partitioning applications between NDP and host CPU cores causes inter-se...
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11/10/2022
DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips
To understand and improve DRAM performance, reliability, security and en...
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11/10/2022
NEON: Enabling Efficient Support for Nonlinear Operations in Resistive RAM-based Neural Network Accelerators
Resistive Random-Access Memory (RRAM) is well-suited to accelerate neura...
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10/08/2022
SpyHammer: Using RowHammer to Remotely Spy on Temperature
RowHammer is a DRAM vulnerability that can cause bit errors in a victim ...
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09/21/2022
HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips
DRAM is the building block of modern main memory systems. DRAM cells mus...
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06/20/2022
Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices
RowHammer is a circuit-level DRAM vulnerability, where repeatedly activa...
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02/04/2022
EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Accelerators
Dilated and transposed convolutions are widely used in modern convolutio...
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01/04/2022
DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators
Random number generation is an important task in a wide variety of criti...
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10/19/2021
A Deeper Look into RowHammer`s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses
RowHammer is a circuit-level DRAM vulnerability where repeatedly accessi...
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06/10/2021
CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations
DRAM is the dominant main memory technology used in modern computing sys...
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06/09/2021
IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors
To operate efficiently across a wide range of workloads with varying pow...
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05/08/2021
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
Data movement between the CPU and main memory is a first-order obstacle ...
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04/15/2021
pLUTo: In-DRAM Lookup Tables to Enable Massively Parallel General-Purpose Computation
Data movement between main memory and the processor is a significant con...
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03/25/2021
Reducing Solid-State Drive Read Latency by Optimizing Read-Retry
3D NAND flash memory with advanced multi-level cell techniques provides ...
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02/11/2021
BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows
Aggressive memory density scaling causes modern DRAM devices to suffer f...
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01/19/2021
SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures
Near-Data-Processing (NDP) architectures present a promising way to alle...
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01/04/2021
Robust Machine Learning Systems: Challenges, Current Trends, Perspectives, and the Road Ahead
Machine Learning (ML) techniques have been rapidly adopted by smart Cybe...
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12/22/2020
Reducing Solid-State Drive Read Latency by Optimizing Read-Retry (Extended Abstract)
3D NAND flash memory with advanced multi-level cell techniques provides ...
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10/06/2020
WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders
Resistive memories have limited lifetime caused by limited write enduran...
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09/18/2020
FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors
Modern client processors typically use one of three commonly-used power ...
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09/17/2020
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching
DRAM Main memory is a performance bottleneck for many applications due t...
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08/25/2020
Optically Connected Memory for Disaggregated Data Centers
Recent advances in integrated photonics enable the implementation of rec...
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05/27/2020
Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques
In order to shed more light on how RowHammer affects modern and future d...
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05/26/2020
CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off
DRAM is the prevalent main memory technology, but its long access latenc...
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10/12/2019
EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM
The effectiveness of deep neural networks (DNN) in vision, speech, and l...
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02/19/2019
Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices
Low-cost devices are now commonplace and can be found in diverse environ...
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08/13/2018
D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput
We propose a new DRAM-based true random number generator (TRNG) that lev...
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08/13/2018